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Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN26562
DESCRIPTION
The Philips Semiconductors SCN26562 Dual Universal Serial Communications Controller (DUSCC) is a single-chip MOS-LSI communications device that provides two independent, multi-protocol, full-duplex receiver/transmitter channels in a single package. It supports bit-oriented and character-oriented (byte count and byte control) synchronous data link controls as well as asynchronous protocols. The SCN26562 interfaces to synchronous bus MPUs and is capable of program-polled, interrupt driven, block-move or DMA data transfers. The operating mode and data format of each channel can be programmed independently. Each channel consists of a receiver, a transmitter, a 16-bit multi-function counter/timer, a digital phase-locked loop (DPLL), a parity/CRC generator and checker, and associated control circuits. The two channels share a common bit rate generator (BRG), operating directly from a crystal or an external clock, which provides 16 common bit rates simultaneously. The operating rate for the receiver and transmitter of each channel can be independently selected from the BRG, the DPLL, the counter/timer, or from an external 1X or 16X clock, making the DUSCC well suited for dual-speed channel applications. Data rates up to 4Mbits per second are supported. The transmitter and receiver each contain a four-deep FIFO with appended transmitter command and receiver status bits and a shift register. This permits reading and writing of up to four characters at a time, minimizing the potential of receiver overrun or transmitter underrun, and reducing interrupt or DMA overhead. In addition, a flow control capability is provided to disable a remote transmitter when the FIFO of the local receiving device is full. Two modem control inputs (DCD and CTS) and three modem control outputs (RTS and two general purpose) are provided. Because the modem control inputs and outputs are general purpose in nature, they can be optionally programmed for other functions. This document contains the electrical specifications for the SCN26562. See SCN26562/SCN68562 User's Guide for complete functional description.
* Parity and FCS (frame check sequence LRC or CRC) generation
and checking
* Programmable data encoding/decoding: NRZ, NRZI, FM0, FM1,
Manchester
* Programmable channel mode: full- and half-duplex, auto-echo, or
local loopback
* Programmable data transfer mode: polled, interrupt, DMA, wait * DMA interface
- Single- or dual-address dual transfers - Half- or full-duplex operation - Automatic frame termination on counter/timer terminal count or DMA EOPN input
* Interrupt capabilities
- Vector output (fixed or modified by status) - Programmable internal priorities - Maskable interrupt conditions
* Multi-function programmable 16-bit counter/timer
- Bit rate generator - Event counter - Count received or transmitted characters - Delay generator - Automatic bit length measurement
* Modem controls
- RTS, CTS, DCD, and up to four general purpose pins per channel - CTS and DCD programmable auto-enables for Tx and Rx - Programmable interrupt on change of CTS or DCD
* On-chip oscillator for crystal * TTL compatible * Single +5V power supply
Asynchronous Mode Features
FEATURES General Features
transmitter
* Dual full-duplex synchronous/asynchronous receiver and * Multiprotocol operation
- BOP: HDLC/ADCCP, SDLC, SDLC loop, X.25 or X.75 link level, etc. - COP: BISYNC, DDCMP - ASYNC: 5-8 bits plus optional parity
* Four character receiver and transmitter FIFOs * 0 to 4Mbit/sec data rate * Programmable bit rate for each receiver and transmitter selectable
from: - 16 fixed rates: 50 to 38.4k baud - One user-defined rate derived from programmable counter/timer - External 1X or 16X clock - Digital phase-locked loop
* Character length: 5 to 8 bits * Odd or even parity, no parity, or force parity * Up to two stop bits programmable in 1/16-bit increments * 1X or 16X and Tx clock factors * Parity, overrun, and framing error detection * False start bit detection * Start bit search 1/2-bit time after framing error detection * Break generation with handshake for counting break characters * Detection of start and end of received break * Character compare with optional interrupt on match * Transmits up to 4Mbit/sec data rate Receives up to 2Mbit/sec data
rate
1995 May 1
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853-0307 15179
Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN26562
Character-Oriented Protocol Features
* Character length: 5 to 8 bits * Odd or even parity, no parity, or force parity * LRC or CRC generation and checking * Optional opening PAD transmission * One or two SYN characters * External sync capability * SYN detection and optional stripping * SYN or MARK line-fill on underrun * Idle in MARK or SYNs * Parity, FCS, overrun, and underrun error detection
BISYNC Features
Bit-Oriented Protocol Features
* Character length: 5 to 8 bits * Detection and transmission of residual character: 0-7 bits * Automatic switch to programmed character length for I field * Zero insertion and detection * Optional opening PAD transmission * Detection and generation of FLAG, ABORT, and IDLE bit patterns * Detection and generation of shared (single) FLAG between
frames
* EBCDIC or ASCII header, text and control messages * SYN, DLE stripping * EOM (end of message) detection and transmission * Auto transparent mode switching * Auto hunt after receipt of EOM sequence (with closing PAD check
after EOT or NAK)
* Detection of overlapping (shared zero) FLAGs * ABORT, ABORT-FLAGs, or FCS FLAGs line-fill on underrun * Idle in MARK or FLAGs * Secondary address recognition including group and global
address
* Control character sequence detection for both transparent and
normal text
* Single- or dual-octet secondary address * Extended address and control fields * Short frame rejection for receiver * Detection and notification of received end of message * CRC generation and checking * SDLC loop mode capability
ORDERING INFORMATION
VCC = +5V +5%, TA = 0C to +70C DESCRIPTION 48-Pin Plastic Dual In-Line Package (DIP) 52-Pin Plastic Leaded Chip Carrier (PLCC) Package Serial Data Rate = 4Mbps Maximum SCN26562C4N48 SCN26562C4A52 DWG # SOT240-1 SOT238-3
ABSOLUTE MAXIMUM RATINGS1
SYMBOL TA TSTG VCC Storage temperature Voltage from VCC to GND3 PARAMETER Operating ambient temperature2 RATING 0 to +70 -65 to +150 -0.5 to +7.0 UNIT C C V
VS Voltage from any pin to ground3 -0.5 to VCC +0.5 V NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. 2. For operating at elevated temperatures, the device must be derated based on +150C maximum junction temperature and thermal resistance of 36C/W junction to ambient for ceramic DIP, 40C/W for plastic DIP, and 42C/W for PLCC. 3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
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Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN26562
PIN CONFIGURATIONS
N PACKAGE
IACKN A3 A2 A1 RTxDAKBN/ GPI1BN IRQN RDYN RTSBN/ SYNOUTBN TRxCB 1 2 3 4 5 6 7 8 9 48 VCC 47 46 45 44 43 42 41 40 39 DIP 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A4 A5 PLCC A6 RTxDAKAN/ GPI1AN X1/CLK X2 RTSAN/ SYNOUTAN TRxCA RTxCA DCDAN/ SYNIAN RxDA TxDA TxDAKAN/ GPI2AN RTxDRQAN/ GPO1AN TxDRQAN/ GPO2AN/RTSAN CTSAN/LCAN D0 D1 D2 D3 EOPN WRN CEN 20 21 TOP VIEW PIN FUNCTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 IACKN A3 A2 A1 RTxDAKBN/ GPI1BN IRQN NC RDYN RTSBN/ SYNOUTBN TRxCB RTxCB DCDBN/ SYNIBN NC RxDB TxDB TxDAKBN/ GPI2BN RTxDRQBN/ GPO1BN TxDRQBN/ GPO2BN/RTSBN CTSBN/LCBN D7 D6 D5 D4 RDN RESETN GND PIN FUNCTION 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 CEN WRN EOPN D3 D2 D1 D0 NC CTSAN/LCAN TxDRQAN/ GPO2AN/RTSAN RTxDRQAN/ GPO1AN TxDAKAN/ GPI2AN TxDA RxDA NC DCDAN/ SYNIAN RTxCA TRxCA RTSAN/ SYNOUTAN X2 X1/CLK RTxDAKAN/ GPI1AN A6 A5 A4 VCC 33 34 INDEX CORNER 8
A PACKAGE
7 1 47 46
RTxCB 10 DCDBN/ 11 SYNIBN RxDB 12 TxDB 13 TxDAKBN/ GPI2BN RTxDRQBN/ GPO1BN TxDRQBN/ GPO2BN/RTSBN CTSBN/LCBN 14 15 16 17
D7 18 D6 19 D5 20 D4 21 RDN 22 RESETN 23 GND 24
SD00203
Figure 1. Pin Configurations
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Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN26562
BLOCK DIAGRAM
CHANNEL MODE AND TIMING A/B DPLL CLK MUX A/B D0-D7 BUS BUFFER DPLLA/B BRG INTERFACE/ OPERATION CONTROL ADDRESS DECODE COUNTER TIMER A/B C/T CLK MUX A/B CTCRA/B RDYN WRN RDN A1-A6 CEN RESETN MPU INTERFACE R/W DECODE DMA CONTROL CCRA/B PCRA/B RSRA/B TRSRA/B ICTSRA/B RTxDRQAN/GPO1AN RTxDRQBN/GPO1BN TxDRQAN/GPO2AN TxDRQBN/GPO2BN RTxDAKAN/GPI1AN RTxDAKBN/GPI1BN TxDAKAN/GPI2AN TxDAKBN/GPI2BN EOPN CONTROL CRC GENERATOR SPEC CHAR GEN LOGIC DMA INTERFACE GSR CMR1A/B CMR2A/B OMRA/B INTERNAL BUS TRANSMIT A/B TRANS CLK MUX TPRA/B TTRA/B TX SHIFT REG TRANSMIT 4 DEEP FIFO CTPRHA/B CTPRLA/B CTHA/B CTLA/B
TxD A/B
TRxCA/B RTxCA/B CTSAN/LCAN CTSBN/LCBN DCDBN/SYNIBN DCDAN/SYNIAN RTSBN/SYNOUTBN RTSAN/SYNOUTAN SPECIAL FUNCTION PINS
RECEIVER A/B RCVR CLK MUX RPRA/B RTRA/B S1RA/B
INTERRUPT CONTROL ICRA/B IRQN IACKN IERA/B IVR IVRM DUSCC LOGIC X1/CLK X2 OSCILLATOR
S2RA/B RxD A/B RCVR SHIFT REG RECEIVER 4 DEEP FIFO CRC ACCUM BISYNC COMPARE LOGIC
SD00204
Figure 2. Block Diagram
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Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN26562
PIN DESCRIPTION
MNEMONIC A1-A6 D0-D7 RDN WRN CEN RDYN IRQN IACKN X1/CLK X2 RESETN RxDA, RxDB TxDA, TxDB RTxCA, RTxCB TRxCA, TRxCB CTSA/BN, LCA/BN DCDA/BN, SYNIA/BN RTxDRQA/BN, GPO1A/BN TxDRQA/BN, GPO2A/BN, RTSA/BN RTxDAKA/BN, GPI1A/BN TxDAKA/BN, GPI2A/BN EOPN RTSA/BN, SYNOUTA/BN VCC GND PIN NO. DIP 4-2, 47-45 31-28, 21-18 22 26 25 7 6 1 43 42 23 37, 12 36, 13 39, 10 40, 9 32, 17 38, 11 34, 15 33, 16 PLCC 4-2, 51-49 33-30, 23-20 24 28 27 8 6 1 47 46 25 40, 14 39, 15 43, 11 44, 10 35, 19 42, 12 37, 17 36, 18 I I/O I I I O O I I I I I O I/O I/O I/O I O O Address lines. Bidirectional data bus. Read strobe. Write strobe. Chip select. Ready. Interrupt request. Interrupt acknowledge. Crystal 1 or external clock. Crystal 2. Master reset. Channel A (B) receiver serial data. Channel A (B) transmitter serial data. Channel A (B) receiver/transmitter clock. Channel A (B) transmitter/receiver clock. Channel A (B) clear-to-send input or loop control output. Channel A (B) data carrier detected or external sync. Channel A (B) receiver/transmitter DMA service request or general purpose output. Channel A (B) transmitter DMA service request, general purpose output or request-to-send. TYPE NAME AND FUNCTION
44, 5 35, 14 27 41, 8 48 24
48, 5 38, 16 29 45, 9 52 26
I I I/O O I I
Channel A (B) receiver/transmitter DMA acknowledge or general purpose input 1. Channel A (B) transmitter DMA acknowledge or general purpose input 2. DMA transfer complete. Channel A (B) request-to-send or Sync detect. Power input. Signal and power ground.
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Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN26562
DC ELECTRICAL CHARACTERISTICS1, 3 TA = 0C to +70C, VCC = 5.0V +5%
SYMBOL VIL VIH VOL VOH IILX1 IIHX1 IILX2 IIHX2 IIL II IOZH IOZL IODL IODH ICC CIN COUT CI/O PARAMETER Input low voltage: All except X1/CLK X1/CLK Input high voltage: All except X1/CLK X1/CLK Output low voltage: All except IRQN IRQN Output high voltage: (Except open drain outputs) X1/CLK input X1/CLK input low current3 high current3 IOL = 5.3mA IOL = 8.8mA IOH = -400A VIN = 0, X2 = GND VIN = VCC, X2 = GND VIN = 0, X1 = open VIN = VCC, X1 = open VIN = 0 VIN = 0 to VCC VIN = VCC VIN = 0 VIN = 0 VIN = VCC VO = 0 to VCC VCC = GND = 0 VCC = GND = 0 VCC = GND = 0 -120 -5 5 275 10 15 20 2.4 -5.5 -100 -40 -5 -5 5 5 -25 0.0 1.0 100 TEST CONDITIONS LIMITS Min Typ Max 0.8 0.4 2.0 2.4 VCC UNIT V V V V V V V mA mA A A A A A A A A A mA pF pF pF
0.5 0.5
X2 input low current3 X2 input high current3 Input low current RESETN, TxDAKN, RxDAKN Input leakage current Output off current high, 3-State data bus Output off current low, 3-State data bus Open drain output low current in off state: EOPN IRQN, RDYN Open drain output high current in off state: EOPN, IRQN, RDYN Power supply current Input capacitance2 Output capacitance2 Input/output capacitance2
NOTES: 1. Parameters are valid over specified temperature range. 2. These values were not explicitly tested; they are guaranteed by design and characterization data. 3. X1/CLK and X2 are not tested with a crystal installed.
AC ELECTRICAL CHARACTERISTICS1, 2, 3, 4 TA = 0C to +70C, VCC = 5V +5%
LIMITS SYMBOL tRELREH PARAMETER RESETN low to RESETN high SCN26562C4 Min 1.2 Max SCN26562C2 Min 1.2 Max s UNIT
NOTES: 1. Parameters are valid over specified temperature range. 2. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.8V and 2.0V with a transition time of 20ns maximum. For X1/CLK, this swing is between 0.4V and 2.4V. All time measurements are referenced at input voltages of 0.4V and 2.4V and output voltages of 1.2V and 2.0V, as appropriate. 3. See Figure 17 for test conditions for outputs. 4. Tests for open drain outputs are intended to guarantee switching of the output transistor. Measurement of this response is referenced from midpoint of the switching signal to a point 0.2V above the actual output signal level. This point represents noise margin that assures true switching has occurred.
RESETN
tRELREH
SD00205
Figure 3. Reset Timing
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Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN26562
AC ELECTRICAL CHARACTERISTICS (Continued)
A6-A1 tADVRDL tRDHCEH CEN tCELRDL tRDLRDH RDN tRDLDDV D0-D7 tRDLRYL RDYN 1 NOTES: 1. Wait on Rx. Receiver FIFO empty. 2. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the `strobing' input. CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated first terminates the cycle. tRYZDDV tRDHDDI tRDHRDL tRDHDDF tRDLADI tCEHCEL
SD00206
Figure 4. Read Cycle
LIMITS SYMBOL tADVRDL tCELRDL tRDLADI tRDLRYL tRDLDDV tRDLRDH tRYZDDV tRDHCEH tCEHCEL tRDHDDI tRDHRDL tRDHDDF PARAMETER Address valid to RDN low CEN low to RDN low RDN low to address invalid RDN low to RDYN low RDN low to read data valid RDN low to RDN high RDYN high impedance to read data valid RDN high to CEN high CEN high to CEN low RDN high to read data invalid RDN high to RDN low RDN high to data bus floating SCN26562C4 Min 10 0 150 300 0 160 10 160 Max SCN26562C2 Min 10 0 150 310 0 170 10 170 Max ns ns ns ns ns ns ns ns ns ns ns ns UNIT
275 280 100
275 300 100
75
75
1995 May 1
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Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN26562
AC ELECTRICAL CHARACTERISTICS (Continued)
A6-A1 tADVWRL tWRHCEH CEN tCELWRL tWRLWRH WRN tWDVWRH D0-D7 tWRLRYL RDYN 1 NOTES: 1. Wait on Tx. Transmitter FIFO full. 2. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the `strobing' input. CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated first terminates the cycle. tWRHWRL tWRHWDI tWRLADI tCEHCEL
SD00207
Figure 5. Write Cycle
LIMITS SYMBOL tADVWRL tCELWRL tWRLRYL tWRHCEH tWRLWRH tWDVWRH tCEHCEL tWRLADI tWRHWRL tWRHWDI PARAMETER Address valid to WRN low CEN low to WRN low WRN low to READY low WRN high to CEN high WRN low to WRN high Write data valid to WRN high CEN high to CEN low WRN low to address invalid WRN high to WRN low WRN high to write data invalid SCN26562C4 Min 10 0 0 300 100 160 150 160 10 Max SCN26562C2 Min 10 0 0 310 100 170 150 170 10 Max ns ns ns ns ns ns ns ns ns ns UNIT
275
275
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Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN26562
AC ELECTRICAL CHARACTERISTICS (Continued)
INTERRUPT REQUEST LOCKED IRQN VECTOR SETTLING IACKN VECTOR LOCKED A A SERVICE ROUTINE Cleared through software
A tIALDDV
D7-D0 B tIAHDDI
C
C
tIAHDDF
NOTES: A ICR[5:4] = 01 or 10 (mode 1 or mode 2) B Call instruction (mode 2) C ICR[5:4] = 11 (mode 3)
SD00208
Figure 6. Interrupt Acknowledge Cycle
LIMITS SYMBOL tIALDDV tIAHDDF tIAHDDI PARAMETER IACKN low to data bus valid IACKN high to data bus floating IACKN high to data bus invalid SCN26562C4 Min Max 280 150 SCN26562C2 Min Max 280 150 ns ns ns UNIT
10
10
CEN
WRN tWRHGOV GPO1_N AND/OR GPO2_N OLD DATA NEW DATA
SD00209
Figure 7. Output Port Timing
LIMITS SYMBOL tWRHGOV PARAMETER WRN high to GPO output data valid SCN26562C4 Min Max 300 SCN26562C2 Min Max 300 ns UNIT
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Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN26562
AC ELECTRICAL CHARACTERISTICS (Continued)
CEN
RDN tGIVRDL tRDLGII GPI1N AND/OR GPI2N
SD00210
Figure 8. Input Port Timing
LIMITS SYMBOL tGIVRDL tRDLGII PARAMETER GPI input valid to RDN low RDN low to GPI input invalid SCN26562C4 Min 20 100 Max SCN26562C2 Min 20 100 Max ns ns UNIT
tCLHCLL tCCHCCL tRCHRCL tTCHTCL X1/CLK CTCLK RxC TxC
tCLLCLH tCCLCCH tRCLRCH tTCLTCH
SD00211
Figure 9. Clock
LIMITS SYMBOL tCLHCLL tCLLCLH tCCHCCL tCCLCCH tRCHRCL tRCLRCH tTCHTCL tTCLTCH fCL fCC fRC fTC PARAMETER Min X1/CLK high to low time X1/CLK low to high time C/T CLK high to low time C/T CLK low to high time RxC high to low time RxC low to high time TxC high to low time TxC low to high time X1/CLK frequency C/T CLK frequency RxC frequency (16X or 1X) TxC frequency (16X or 1X) 25 25 100 100 110 110 110 110 2.0 0 0 0 SCN26562C4 Typ Max Min 25 25 100 100 150 150 150 150 2.0 0 0 0 SCN26562C2 Typ Max ns ns ns ns ns ns ns ns MHz MHz MHz MHz UNIT
14.7456
16.0 4.0 4.0 4.0
14.7456
16.0 4.0 2.5 2.5
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Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN26562
AC ELECTRICAL CHARACTERISTICS (Continued)
1 BIT TIME (1 OR 16 CLOCKS) TxC (INPUT) tCILTXV TxD tCOLTXV TxC (1X OUTPUT)
SD00212
Figure 10. Transmit Timing
LIMITS SYMBOL tCILTXV tCOLTXV PARAMETER TxC input low (1X) to TxD output TxC input low (16X) to TxD output TxC output low to TxD output SCN26562C4 Min Max 240 435 50 SCN26562C2 Min Max 240 435 50 ns ns ns UNIT
tRCHSOL
SYNOUTN tSILRCH SYNIN tRCHSIH
RXC (1X) INPUT tRXVRCH RxD tRCHRXI
SD00213
Figure 11. Receive Timing
LIMITS SYMBOL tRXVRCH tRCHRXI PARAMETER RxD data valid to RxC high: For NRZ data For NRZI, Manchester, FM0, FM1 data RxC high to RxD data invalid: For NRZ data For NRZI, Manchester, FM0, FM1 data SYNIN low to RxC high RxC high to SYNIN high RxC high to SYNOUT low SCN26562C4 Min 50 120 50 10 100 50 Max SCN26562C2 Min 50 130 50 10 100 50 Max ns ns ns ns ns ns ns UNIT
tSILRCH tRCHSIH tRCHSOL
300
300
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Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN26562
AC ELECTRICAL CHARACTERISTICS (Continued)
tWRHEOZ EOPN (OUTPUT)
tWRLEOL
RTxDRQN OR TxDRQN
CEN
tWRLTRH A WRN
D7-D0 tEILWRH EOPN (INPUT) tWRHEIH
A
The TxFIFO is addressed during this write cycle.
SD00214
Figure 12. Transmit Dual Address DMA Timing
LIMITS SYMBOL tWRLTRH tWRLEOL tWRHEOZ tEILWRH tWRHEIH PARAMETER WRN low to Tx DMA REQN high WRN low to EOPN output low WRN high to EOPN output high impedance EOPN input low to WRN high WRN high to EOPN input high SCN26562C4 Min Max 320 225 225 SCN26562C2 Min Max 320 225 225 ns ns ns ns ns UNIT
50 50
50 50
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Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN26562
AC ELECTRICAL CHARACTERISTICS (Continued)
RTxDRQN
tRDLRRH
CEN
RDN
A
D7-D0
tRDLEOL EOPN (OUTPUT)
tRDHEOZ
A
The RxFIFO is addressed during this read cycle.
SD00215
Figure 13. Receive Dual Address DMA Timing
LIMITS SYMBOL tRDLRRH tRDLEOL tRDHEOZ PARAMETER RDN low to Rx DMA REQN high RDN low to EOPN output low RDN high to EOPN output high impedance SCN26562C4 Min Max 320 300 225 SCN26562C2 Min Max 320 300 225 ns ns ns UNIT
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Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN26562
AC ELECTRICAL CHARACTERISTICS (Continued)
TxRQN tTAHTAL TxDAKN tTALTAH tTALTRH
WRN A
MEMRN B tEILTAH EOPN (INPUT) tWDVTAH tTAHWDI tTAHEIH
D7-D0 tTAHEOF tTALEOL EOPN (OUTPUT)
NOTES: A Ignored by the DUSCC since CEN is not asserted, but it can be used externally to qualify TxDAKN. B Memory read signal; not seen by DUSCC.
SD00216
Figure 14. DMA-Transmit Single Address Mode
LIMITS SYMBOL tTAHTAL tTALTAH tTALTRH tWDVTAH tTAHWDI tTALEOL tTAHEOF tEILTAH tTAHEIH PARAMETER Transmit DMA ACKN high to low time Transmit DMA ACKN low to high time Tx DMA ACKN low to Tx DMA REQN high Write data valid to Tx DMA ACKN high Tx DMA ACKN high to write data invalid Tx DMA ACKN low to EOPN output low Tx DMA ACKN high to EOPN output float EOPN input low to Tx DMA ACKN high Tx DMA ACKN high to EOPN input high SCN26562C4 Min 100 250 90 30 50 50 250 170 200 Max SCN26562C2 Min 100 250 90 30 50 50 250 170 200 Max ns ns ns ns ns ns ns ns ns UNIT
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Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN26562
AC ELECTRICAL CHARACTERISTICS (Continued)
RxDRQN tRAHRAL RxDAKN tRALRAH tRALRRH
RDN A
MEMWN B tRALEOL EOPN (OUTPUT) tRALDDV tRAHDDI tRAHEOF
D7-D0 tRAHDDF NOTES: A Ignored by the DUSCC bit; it can be used to qualify RxDAKN. B Memory read signal; not seen by DUSCC.
SD00217
Figure 15. DMA-Receive Single Address Mode
LIMITS SYMBOL tRAHRAL tRALRAH tRALRRH tRALEOL tRAHEOF tRALDDV tRAHDDI tRAHDDF PARAMETER Receive DMA ACKN high to low time Receive DMA ACKN low to high time Rx DMA ACKN low to Rx DMA REQN high Rx DMA ACKN low to EOPN output low Rx DMA ACKN high to EOPN output float Rx DMA ACKN low to read data valid Rx DMA ACKN high to read data invalid Rx DMA ACKN high to data bus float SCN26562C4 Min 160 250 Max SCN26562C2 Min 160 250 Max ns ns ns ns ns ns ns ns UNIT
320 200 225 225 125
320 200 225 225 125
10
10
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Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN26562
AC ELECTRICAL CHARACTERISTICS (Continued)
RDN/WRN tRWHIRH IRQN VM VOL +0.2V VOL
SD00218
Figure 16. Interrupt Timing
LIMITS SYMBOL PARAMETER RDN/WRN high to IRQN high for: Read RxFIFO (RxRDY interrupt) Write TxFIFO (TxRDY interrupt) Write RSR (Rx condition interrupt) Write TRSR (Rx/Tx interrupt) Write ICTSR (counter/timer interrupt) SCN26562C4 Min Max 450 450 400 400 400 SCN26562C2 Min Max 450 450 400 400 400 ns ns ns ns ns UNIT
tRWHIRH
X1/CLK
WRN
COMMAND VALID
SD00219
Figure 17. Command Timing
RxC
1
2
3
4
5
6
7
8
RxD
LCN a. Loop Control Output Assertion
RxC
1
2
3
4
5
6
7
8
9
RxD
LCN b. Loop Control Output Negation
SD00220
Figure 18. Relationship Between Received Data and the Loop Control Output
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Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN26562
2.7K IRQN 50pF VDD
820 RDYN 150pF +5.0V
1K EOPN 50pF VDD
710 ALL OTHER OUTPUTS 150pF +5.0V
NOTE: All CL includes 50pF stray capacitance, i.e., CL = 150pF = 100pF discrete +50pF stray.
SD00221
Figure 19. Test Conditions for Outputs
1995 May 1
17

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Price & Availability of SCN26562

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